Research

Fault Modeling
  • Functional Fault Model of High Correlation with Stuck-at Fault Model
  • Functional Fault Model of High Correlation with Real Defects
  • New Fault Model for New CMOS Technology¬† (1 vacancy for research assistant /¬† research student)
Test Generation
  • High Level Constraint Driven Test Generation Techniques
  • Software-based Self-Testing for Processors
Design for Testability
  • Non-Scan Technique based on Thru Testability
  • High Level Design-for-Testability for Assignment Decision Diagrams
  • High Level Built-in Self-Test for Assignment Decision Diagrams
System-on-Chip Design and Test
  • Test Scheduling under Power Constraint (supported by UTM Research University Grant, April 2011 to Mac 2012)
  • System-on-Chip Design and Testing for Image Processing (supported by MJIIT Research Grant, August 2011 to July 2014)
  • Test Scheduling for Network-on-Chip (supported by ScienceFund, 2012 to 2013)
  • Online Testing for Network-on-Chip (supported by Intel Research Grant, 2011 to 2012)
  • Thermal-Aware Testing (supported by UTM Research University Grant, 2012 to 2013) (1 vacancy for research assistant /¬† research student)
Verification
  • Verification Platform using High Level Fault Modeling
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