**Journal**Year | Title | Journal | Authors |

2012 | Power-Aware System-on-Chip Test Scheduling using Enhanced Rectangle Packing Algorithm | Computers and Electrical EngineeringPage 1444-14552011 IF=0.837 | Chia Yee Ooi Jia Pao Sua Siaw Chen Lee |

2011 | A New Design-for-Testability Method based on Thru-Testability | Journal of Eletronic Testing: Theory and Application: Volume 27, Issue 5 (2011), Page 583-598DOI: 10.1007/s10836-011-5241-8 2010 IF=0.5 | Chia Yee Ooi Hideo Fujiwara |

June 2010 | A New Class of Easily Testable Assignment Decision Diagrams | Malaysian Journal of
Computer Science Vol. 23, No. 1, pp. 1-17 Scopus-indexed(2010 IF=0.364 announced in 2011) | Norlina Paraman Chia Yee Ooi Ahmad Zuri Sha'ameri Hideo Fujiwara |

December 2009 | Test
Generation for Sequential
Circuits with Partial Thru
Testability (In Japanese) | Trans.
of IEICE on Information
and
Systems Vol.J92-D, No.12, pp. 2207-2216 2008 IF=0.369 | Nobuya
Oka Chia Yee Ooi Hideyuki Ichihara Tomoo Inoue Hideo Fujiwara |

September 2008 | A Non-Scan Design-for-Testability for Register-Transfer Level Circuits to Guarantee Linear-Depth Time Expansion Models | IEEE Trans. on Computer-Aided Design
of Integrated Circuits
and Systems pp. 1535-1544
2007 IF=0.776 | Hideo Fujiwara Hiroyuki Iwata Tomokazu Yoneda Chia Yee Ooi |

August 2007 | Analysis
of Test Generation Complexity
for Stuck-At and
Path Delay Faults Based on t^{k}-Notation | Trans. of IEICE on
Information and
Systems pp. 1202-1212
2006 IF=0.28 | Chia Yee Ooi Thomas Clouqueur Hideo Fujiwara |

December 2005 | Classification
of Sequential Circuits Based on t^{k}Notation
and Its Applications | Trans.
of IEICE
on Information and Systems pp. 2738-2747
2004 IF=0.274 | Chia Yee Ooi Thomas Clouqueur Hideo Fujiwara |

**Conference**Year | Title | Conference | Authors |

2011 | nth-Level Network Partitioning in Network-on-Chip | 4^{th} Engineering Conference | Asrani Lit Muhammad Nadzir Marsono Hazrul Mohamed Basri Shaikh Nasir Shaikh Husin Chia Yee Ooi |

2011 | A Network-on-Chip Simulation Framework for Homogeneous Multi-Processor System-on-Chip | IEEE 9^{th} International Conference on ASIC | Yuan Wen Hau M. N. Marsono Chia Yee Ooi M. Khalil-Hani |

2011 | Multi-TAP Architecture for IP Testing and Debugging on Network-on-Chips | TENCON | Selva Rajagopal Mahdieh Nadi Senejani Chia Yee Ooi Muhammad Nadzir Marsono |

2011 | Built-in Self-Test for Functional Register-Transfer Level using Assignment Decision Diagram | 12^{th} Workshop on RTL and High Level Testing | Norlina Paraman Chia Yee Ooi A. Z. sha'ameri Hideo Fujiwara |

2010 | Functional Fault Model for Micro Operation Faults of High Correlation with Stuck-At Faults | 11^{st} Workshop on RTL and
High Level Testing | Chia Yee Ooi Hideo Fujiwara |

2009 | Test Generation and DFT Based on Partial Thru Testability | IEEE European Test Symposium Poster session | Nobuya
Oka Chia Yee Ooi Hideyuki Ichihara Tomoo Inoue Hideo Fujiwara |

2008 | Enhancement of Test Environment Generation for Assignment Decision Diagrams | 9^{th} Workshop on RTL and
High Level Testingpp. 45-50 | Hideo
Fujiwara Chia Yee Ooi Y. Shimizu |

2008 | A New Class of Easily Testable Assignment Decision Diagrams | 9^{th} Workshop on RTL and
High Level Testingpp. 51-56 | Norlina
Paraman Chia Yee Ooi A. Z. Sha'ameri Hideo Fujiwara |

2007 |
An
Extended Class of
Acyclically Testable Circuits
| 8^{th} Workshop on RTL and
High Level Testingpp. 17-22 | Nobuya
Oka Chia Yee Ooi Hideyuki Ichihara Tomoo Inoue Hideo Fujiwara |

2006 | A New Class of Sequential Circuits with Acyclic Test Generation Complexity | 4^{th}
IEEE International Conference on Computer Designpp. 425-431 | Chia Yee Ooi Hideo Fujiwara |

2006 | A New Scan Design Technique Based on Pre-Synthesis Thru Functions |
15^{th}
IEEE Asian Test Symposium | Chia Yee Ooi Hideo Fujiwara |

2005 |
Test Generation
Complexity for Path Delay Faults Based on t^{k}-Notation |
6^{th} Workshop on RTL and High Level
Testingpp. 61-72 | Chia Yee Ooi Thomas Clouqueur Hideo Fujiwara |

2004 |
Classification of
Sequential Circuits Based on t^{k}-Notation |
13^{th}
IEEE Asian Test Symposium pp. 348-353 | Chia Yee Ooi Hideo Fujiwara |