Publication

Journal

 YearTitle
 JournalAuthors
 2012 Power-Aware System-on-Chip Test Scheduling using Enhanced Rectangle Packing Algorithm

Computers and Electrical Engineering
Page 1444-1455
2011 IF=0.837

Chia Yee Ooi
Jia Pao Sua
Siaw Chen Lee
 2011 A New Design-for-Testability Method based on Thru-Testability

Journal of Eletronic Testing: Theory and Application:
Volume 27, Issue 5 (2011), Page 583-598
DOI: 10.1007/s10836-011-5241-8
2010 IF=0.5

Chia Yee Ooi
Hideo Fujiwara
 
June
2010
 A New Class of Easily Testable Assignment Decision DiagramsMalaysian Journal of Computer Science
Vol. 23, No. 1, pp. 1-17
Scopus-indexed
(2010 IF=0.364 announced in 2011)
Norlina Paraman
Chia Yee Ooi
Ahmad Zuri Sha'ameri
Hideo Fujiwara
December 2009
Test Generation for Sequential Circuits with Partial Thru Testability (In Japanese)
Trans. of IEICE on Information and Systems
Vol.J92-D, No.12, pp. 2207-2216
2008 IF=0.369
Nobuya Oka
Chia Yee Ooi
Hideyuki Ichihara Tomoo Inoue
Hideo Fujiwara
September 2008
A Non-Scan Design-for-Testability for Register-Transfer Level Circuits to Guarantee Linear-Depth Time Expansion ModelsIEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
pp. 1535-1544
2007 IF=0.776

Hideo Fujiwara
Hiroyuki Iwata
Tomokazu Yoneda
Chia Yee Ooi
August 2007
Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on tk-NotationTrans. of IEICE on Information and Systems
pp. 1202-1212
2006 IF=0.28

Chia Yee Ooi
Thomas Clouqueur Hideo Fujiwara
December 2005
Classification of Sequential Circuits Based on tkNotation and Its ApplicationsTrans. of IEICE on Information and Systems
pp. 2738-2747
2004 IF=0.274

Chia Yee Ooi
Thomas Clouqueur Hideo Fujiwara
Conference

 YearTitle
 ConferenceAuthors
2011nth-Level Network Partitioning in Network-on-Chip

4th Engineering Conference Asrani Lit
Muhammad Nadzir Marsono
Hazrul Mohamed Basri
Shaikh Nasir Shaikh Husin
Chia Yee Ooi
2011A Network-on-Chip Simulation Framework for Homogeneous Multi-Processor System-on-ChipIEEE 9th International Conference on ASIC

Yuan Wen Hau
M. N. Marsono
Chia Yee Ooi
M. Khalil-Hani
2011Multi-TAP Architecture for IP Testing and Debugging on Network-on-ChipsTENCONSelva Rajagopal
Mahdieh Nadi Senejani
Chia Yee Ooi
Muhammad Nadzir Marsono
2011

Built-in Self-Test for Functional Register-Transfer Level using Assignment Decision Diagram12th Workshop on RTL and High Level TestingNorlina Paraman
Chia Yee Ooi
A. Z. sha'ameri
Hideo Fujiwara
2010Functional Fault Model for Micro Operation Faults of High Correlation with Stuck-At Faults

11st Workshop on RTL and High Level Testing
Chia Yee Ooi
Hideo Fujiwara
2009Test Generation and DFT Based on Partial Thru TestabilityIEEE European Test Symposium
Poster session
Nobuya Oka
Chia Yee Ooi
Hideyuki Ichihara Tomoo Inoue
Hideo Fujiwara
2008 Enhancement of Test Environment Generation for Assignment Decision Diagrams9th Workshop on RTL and High Level Testing
pp. 45-50
Hideo Fujiwara
Chia Yee Ooi
Y. Shimizu
2008A New Class of Easily Testable Assignment Decision Diagrams9th Workshop on RTL and High Level Testing
pp. 51-56
Norlina Paraman
Chia Yee Ooi
A. Z. Sha'ameri
Hideo Fujiwara
2007 An Extended Class of Acyclically Testable Circuits
8th Workshop on RTL and High Level Testing
pp. 17-22
 Nobuya Oka
Chia Yee Ooi Hideyuki Ichihara Tomoo Inoue
Hideo Fujiwara
2006
A New Class of Sequential Circuits with Acyclic Test Generation Complexity4th IEEE International Conference on Computer Design
pp. 425-431
Chia Yee Ooi
Hideo Fujiwara
2006
A New Scan Design Technique Based on Pre-Synthesis Thru Functions 15th IEEE Asian Test Symposium Chia Yee Ooi
Hideo Fujiwara
2005
Test Generation Complexity for Path Delay Faults Based on tk-Notation 6th Workshop on RTL and High Level Testing
pp. 61-72
Chia Yee Ooi
Thomas Clouqueur Hideo Fujiwara
2004
Classification of Sequential Circuits Based on tk-Notation 13th IEEE Asian Test Symposium
pp. 348-353
Chia Yee Ooi
Hideo Fujiwara

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