Welcome to my Website!

Hi, my name is Ooi Chia Yee. Ooi is my family name, which is pronounced Huáng in Pinyin and written as 黄 in Chinese character. I was born in 1979, living at Skudai, Johor, Malaysia. My hometown is Alor Star, Kedah, Malaysia and my ancestral home is Fujian in China (福建省南安市梅山镇灯埔村).

I am working as a senior lecturer at Faculty of Electrical Engineering (a.k.a. FKE), Universiti Teknologi Malaysia. I teach courses related to digital system design and test. Basic electronics, digital electronic, digital system, integrated circuit testing techniques are among the courses I have taught since year 2003. They are fundamental and advanced courses important in VLSI realization flow.  My research field of interest includes design for testability, test generation complexity, synthesis for testability, system-on-chip test and verification.
You could get more details about my teaching and research from this website.

Starting from June 2011, I am seconded to the Malaysia-Japan International Institute of Technology at International Campus of Universiti Teknologi Malaysia located at Kuala Lumpur. I am currently in charge of the postgraduate programme matters. If you are interested to know more about the programmes offered here, please visit www.mjiit.utm.my or write to mjiit at ic.utm.my